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| 2W PACKAGED POWER PHEMT * FEATURES 32.5 dBm Linear Output Power 17 dB Power Gain at 2 GHz 9.5 dB Maximum Stable Gain at 10 GHz 42 dBm Output IP3 45% Power-Added Efficiency at 2 GHz FPD3000P100 * DESCRIPTION AND APPLICATIONS The FPD3000P100 is a packaged AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (PHEMT), featuring a 0.25 m by 3000 m Schottky barrier gate, defined by highresolution stepper-based photolithography. The recessed and offset Gate structure minimizes parasitics to optimize performance. The epitaxial structure and processing have been optimized for reliable high-power applications. The FPD3000P100 also features Si3N4 passivation and is also available in die form and in the low cost plastic SOT89 plastic package. Typical applications include commercial and other narrowband and broadband high-performance amplifiers, including SATCOM uplink transmitters, PCS/Cellular low-voltage high-efficiency output amplifiers, and medium-haul digital radio transmitters. * ELECTRICAL SPECIFICATIONS AT 22C Parameter Power at 1dB Gain Compression Power Gain at P1dB Maximum Stable Gain (S21/S12) Symbol P1dB G1dB SSG Test Conditions VDS = 8 V; IDS = 50% IDSS VDS = 8 V; IDS = 50% IDSS VDS = 8 V; IDS = 50% IDSS f = 2 GHz f = 10 GHz Power-Added Efficiency Output Third-Order Intercept Point (from 15 to 5 dB below P1dB) Saturated Drain-Source Current Maximum Drain-Source Current Transconductance Gate-Source Leakage Current Pinch-Off Voltage Gate-Drain Breakdown Voltage Thermal Resistivity (see Notes) IDSS IMAX GM IGSO |VP| |VBDGD| JC PAE IP3 VDS = 8 V; IDS = 50% IDSS; POUT = P1dB VDS = 8V; IDS = 50% IDSS Matched for optimal power VDS = 1.3 V; VGS = 0 V VDS = 1.3 V; VGS +1 V VDS = 1.3 V; VGS = 0 V VGS = -5 V VDS = 1.3 V; IDS = 3 mA IGD = 3 mA VDS > 6V 0.7 14.5 750 42 930 1.5 800 2 1.0 16.0 24 20 1.3 1110 dBm mA A mS A V V C/W 20.5 8.5 21.5 9.5 45 dB dB % Min 31.0 16.5 Typ 32.5 17.0 Max Units dBm dB UNLESS OTHERWISE NOTED, RF SPECIFICATIONS MEASURED AT f = 2 GHz USING CW SIGNAL Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis Released: 6/27/05 Email: sales@filcsi.com 2W PACKAGED POWER PHEMT * * RECOMMENDED BIAS CONDITIONS: Drain-Source Voltage: 5V to 8V Drain-Source Current: 33% to 50% IDSS ABSOLUTE MAXIMUM RATINGS1 Parameter Drain-Source Voltage Gate-Source Voltage Drain-Source Current Gate Current RF Input Power 2 FPD3000P100 Symbol VDS VGS IDS IG PIN TCH TSTG PTOT Comp. 3 2 Test Conditions -3V < VGS < +0V 0V < VDS < +8V For VDS > 2V Forward or reverse current Under any acceptable bias state Under any acceptable bias state Non-Operating Storage See De-Rating Note below Under any bias conditions 2 or more Max. Limits Min Max 9 -3 IDSS 25 600 175 Units V V mA mA mW C C W dB % Channel Operating Temperature Storage Temperature Total Power Dissipation Gain Compression Simultaneous Combination of Limits 1 3 -40 150 5.3 5 80 Users should avoid exceeding 80% of 2 or more Limits simultaneously TAmbient = 22C unless otherwise noted Max. RF Input Limit must be further limited if input VSWR > 2.5:1 Notes: * Operating conditions that exceed the Absolute Maximum Ratings could result in permanent damage to the device. * Thermal Resitivity specification assumes a Au/Sn eutectic die attach onto a Au-plated copper heatsink or rib. * Power Dissipation defined as: PTOT (PDC + PIN) - POUT, where PDC: DC Bias Power PIN: RF Input Power POUT: RF Output Power * Absolute Maximum Power Dissipation to be de-rated as follows above 22C: PTOT= 5.3W - (0.042W/C) x THS where THS = heatsink or ambient temperature above 22C Example: For a 85C heatsink temperature: PTOT = 5.3W - (0.042 x (85 - 22)) = 2.65 * HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 0 (< 250V) per JESD22-A114-B, Human Body Model, and Class A (< 200V) per JESD22-A115-A, Machine Model. Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis Released: 6/27/05 Email: sales@filcsi.com 2W PACKAGED POWER PHEMT * APPLICATIONS NOTES & DESIGN DATA Applications Notes are available from your local Filtronic Sales Representative or directly from the factory. Complete design data, including S-parameters, noise data, and large-signal models are available on the Filtronic web site. RECOMMENDED BIASING GUIDELINES: For most applications, a dual-bias circuit is required due to the amount of quiescent current drawn by the FPD3000P100. The Source of the discrete pHEMT device is wire-bonded to the package flange, and therefore self-biasing (using a bypassed Source resistor to set the Gate-Source voltage) is not practical. A dual-bias circuit will require a regulated and filtered negative Gate supply as well as a positive Drain supply. Typical Gate bias voltages will be about -0.4V. Active bias circuits can be employed if the dissipation by a Drain current sense resistor is acceptable, and in these cases the bias voltages must be sequenced so that the negative Gate voltage is established at its final value before the Drain voltage is reached, to prevent device self-oscillation. FPD3000P100 * All information and specifications are subject to change without notice. Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis Released: 6/27/05 Email: sales@filcsi.com |
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